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FAQs: DARPA Circuit Realization At Faster Timescales (CRAFT) Program (BAA 15-55)

What is DARPA's CRAFT program?

CRAFT (Circuit Realization At Faster Timescales) is a DARPA Microsystems Technology Office research and development program focused on modernizing how custom integrated circuits (ICs) are designed and transitioned to manufacturing. The core idea is to create a new, practical design flow and supporting methodology that makes high-performance custom chip development dramatically faster and less labor-intensive than traditional approaches.

What problem is this opportunity trying to solve?

The opportunity targets the slow, highly specialized, and labor-intensive nature of advanced custom silicon development. DARPA is looking for ways to reduce time, specialized human effort, and repeated hand-tuning while still preserving the performance advantages of custom ICs.

What is the central goal of CRAFT?

The central goal is to develop a practical design flow and methodology that compresses custom IC development timelines and reduces manual effort, without sacrificing the high performance typically associated with custom chip design.

What technical outcomes define success for the program?

The opportunity describes three outcomes that define success:

• Sharply reducing the effort required to design high-performance custom ICs.
• Making it much easier to port IC designs to alternate foundries and/or to newer process nodes.
• Increasing reuse of integrated circuit elements (IP reuse) through more modular and composable design elements.

What does "reduce the effort required to design high-performance custom ICs" mean in this context?

It points to improved automation, better tooling, and more structured design methodologies that reduce manual steps, redesign cycles, and the need for highly specialized, time-consuming circuit-level optimization for each new chip.

Why is porting designs across foundries or process nodes a focus area?

Moving a design between foundries or migrating to a newer process node often requires extensive rework due to differences in process design kits (PDKs), device characteristics, design rules, and available IP. CRAFT signals interest in approaches that reduce this friction so designs can be retargeted more quickly and with fewer redesign iterations.

What does DARPA mean by "IP reuse" for integrated circuits?

IP reuse refers to reusing circuit elements and design building blocks across projects and process targets. The program emphasizes more modular, composable elements that can be reliably reused rather than rebuilt or heavily modified each time.

Is CRAFT primarily about creating new chip designs, or improving the design process itself?

Based on the description, CRAFT is centered on improving the design flow and methodology for custom IC development and manufacturing transition, with an emphasis on speed, reduced labor, portability, and reuse.

Which DARPA office is sponsoring this opportunity?

The opportunity is sponsored by DARPA's Microsystems Technology Office (MTO).

What type of funding opportunity is this?

This is a discretionary federal funding opportunity under the Science and Technology and other Research and Development category, identified as DARPA BAA 15-55.

What is the CFDA number associated with this opportunity?

The summary lists CFDA 12.910 (Research and Technology Development).

What funding instruments may DARPA use for awards under this opportunity?

The listed funding instruments include cooperative agreements, grants, and other procurement contracts. This indicates DARPA may choose different award structures depending on the proposed work and the level of expected collaboration and oversight.

Who is eligible to apply?

The opportunity is listed as open to unrestricted applicants, meaning it is broadly available to qualified organizations, subject to any eligibility clarifications in the full solicitation.

Is cost sharing or matching required?

No cost-sharing or matching requirement is stated in the summary information provided.

When was this opportunity posted?

The posting date is August 17, 2015.

What was the application closing date?

The original and current closing date shown is October 5, 2015.

Is this opportunity still active?

The summary indicates an archive date of April 5, 2016, and the closing date is October 5, 2015, so it is presented as a past/archived opportunity.

How much funding is available per award?

The award floor and ceiling are shown as 0 in the summary record. This usually means the specific funding levels were not captured in that field and would be described in the full announcement or determined through the proposal and negotiation process.

Where can applicants find the full announcement?

The summary references access through the DARPA solicitations page, where the full announcement for DARPA BAA 15-55 would typically be provided.

Who is the point of contact listed for access issues related to the full announcement?

The listed point of contact for access issues is Dr. Linton Salmon, Program Manager in DARPA's Microsystems Technology Office, referenced through the DARPA solicitations page.

What is DARPA hoping to change about custom chip development overall?

CRAFT is described as an effort to make custom chip creation faster and more repeatable by reducing dependence on slow, bespoke practices; enabling smoother transitions across foundries and process generations; and building a foundation for reusable circuit IP that can be adapted and deployed with far less re-engineering.