NSF NRI Graduate Student and Postdoctoral Fellow Supplements to NSF Centers in Nanoelectronics (NSF 10 031) | Apply Online

Frequently Asked Questions (FAQs) - NSF PD 10-031 Supplemental Funding Opportunity

What is NSF PD 10-031?

NSF PD 10-031 is a discretionary supplemental funding opportunity from the National Science Foundation (NSF). It is tied to existing NSF-funded nanoelectronics centers and was created through a cooperative effort between NSF and the Semiconductor Industry Association (SIA) via the Nanoelectronics Research Initiative (NRI).

Is this opportunity for brand-new projects or existing NSF awards?

This opportunity is for supplements to ongoing, long-term center research supported by NSF. It is not intended to fund brand-new standalone projects; instead, it adds targeted support to work already being conducted within eligible NSF nanoelectronics centers.

What is the main purpose of these supplements?

The supplements are intended to strengthen and accelerate center research and education in nanoelectronics by providing additional funds specifically to support added graduate students and postdoctoral fellows. The goal is also to deepen day-to-day links between university-based center research and industry perspectives through collaboration with NRI company assignees.

What types of costs or activities are these supplemental funds meant to support?

Based on the description, the supplemental funds are specifically aimed at bringing in additional graduate students and postdoctoral fellows who will contribute to the center's research in a collaborative environment involving NRI industry assignees.

Why was this supplement program created (what problem is it trying to address)?

The program is motivated by the growing difficulty of continuing performance gains through traditional CMOS scaling. As CMOS approaches fundamental scaling limits, power density and heat become dominant constraints, making it harder to improve speed and efficiency simply by shrinking transistors. The supplements are designed to encourage exploratory, high-impact work on concepts that could succeed CMOS.

How does this opportunity connect NSF and industry?

The opportunity is part of a cooperative effort between NSF and SIA through NRI. Trainees supported by the supplement are expected to work in a collaborative setting that includes participating NRI company assignees, strengthening practical, day-to-day connections between academic center research and industry views on future nanoelectronics needs.

What is the key research direction this program is looking for?

A central requirement is alignment with NRI goals, particularly the search for a novel logic switch that is not based on a field-effect transistor (a non-FET approach) and could serve as a successor to CMOS. NRI emphasizes device and computing concepts that use computational state variables other than the conventional FET method of controlling electronic charge using an electrostatic potential barrier.

Does the supplement support incremental improvements to conventional transistors?

The description emphasizes credible paths to computation that are not just incremental improvements to the standard transistor paradigm. The stated focus is on non-FET logic switch concepts that could succeed CMOS.

What does "alignment in two directions at once" mean for a supplement request?

The proposed supplemental work must align in two ways: (1) it must be consistent with the mission and goals of the NSF center that would receive the supplement, and (2) it must align with NRI goals, especially work aimed at non-FET successor concepts to CMOS.

What topical areas were highlighted as priorities for this supplement cycle?

NRI highlighted three areas of particular interest:

• Circuit architectures that can perform computation using non-FET devices.
• Directed self-assembly and bottom-up fabrication approaches aimed at constructing specific non-FET device structures.
• Nanoengineering of phonon flow in non-FET devices and circuits, with emphasis on heat control, thermal transport, and potentially enabling non-equilibrium behavior.

Why is thermal management and power emphasized in the research scope?

The opportunity ties thermal considerations directly to the CMOS scaling bottleneck: increasing power density is described as the primary limitation to continued scaling. Proposed devices and architectures are therefore expected to focus on achieving low energy consumption while maintaining high computational speed.

Who is the intended participant group supported by the supplement?

The opportunity specifically targets support for additional graduate students and postdoctoral fellows (trainees) who will work within NSF nanoelectronics centers in collaboration with NRI industry assignees.

What kind of research environment is expected for trainees funded under this supplement?

Trainees are expected to work in a collaborative setting that includes participating NRI company assignees. This is meant to strengthen the day-to-day linkage between university-based center research and industry perspectives.

Is this a cost-sharing program?

No. The opportunity is described as a discretionary NSF grant supplement mechanism and explicitly notes that it is not a cost-sharing program.

Which NSF program areas or disciplines does this opportunity relate to?

The opportunity is listed under multiple NSF CFDA areas, reflecting its multidisciplinary nature, including:

• Engineering (47.041)
• Mathematical and Physical Sciences (47.049)
• Computer and Information Science and Engineering (47.070)

What were the key dates for this opportunity?

The posting date was April 1, 2010. The supplement due date was May 10, 2010, by 5 p.m. local time.

The listing shows expected awards and total funding as 0. What does that indicate?

The synopsis shows expected awards and estimated total funding as 0. Based on the description provided, this typically indicates that awards are contingent on available funds and qualifying supplement requests rather than a fixed, pre-announced funding pool in the public listing.

Who is eligible to apply?

The synopsis describes eligibility as unrestricted. However, the program description makes clear that the supplements are intended for NSF centers engaged in long-term nanoelectronics research that can host graduate student or postdoctoral work in collaboration with NRI industry assignees.

What additional documents were referenced for more details?

Additional program details were provided through a related Dear Colleague Letter (NSF 10-013). The description also notes that examples of prior supplement awards were available through NSF nano-related award listings.

Where is support directed for access issues related to applying?

Contact support for access issues is routed through NSF's grants.gov support channel.